The invention relates to a semiconductor device with a MOS transistor of the depletion type comprising a semiconductor body with a substrate of a first conductivity type provided with a layer of the opposed, the second conductivity type adjoining a surface of said semiconductor body, in which layer a source zone of the second conductivity type, a drain zone of the second conductivity type, and an interposed channel region of the second conductivity type are defined, while a gate electrode is provided above the channel region, electrically insulated therefrom by an insulating layer, and the semiconductor body is further provided with a zone of the first conductivity type which forms a pn junction with the channel region and which adjoins the surface for the removal of minority charge carriers from the channel region. Such a device is known inter alia from the patent document U.S. Pat. No. 4,868,620.
Such transistors, often referred to as deep depletion MOST, may be used to advantage in high-voltage circuits, for example for deriving a lower voltage from the high supply voltage while connected as a source follower, which lower voltage may be used as a supply voltage for a low-voltage portion which is often present in an integrated high-voltage circuit.
In the semiconductor device known from the US patent cited above, the semiconductor layer adjoining the surface is formed by an n-type epitaxial silicon layer provided on a p-type silicon substrate. An island is defined in the epitaxial layer by deep p-type insulation zones, in which island the source and drain are formed as strongly doped n-type zones, separated from one another by an n-type channel region with a lower doping level and an adjoining drift region. A gate electrode, separated from the channel by an oxide layer, is provided above the channel layer.
The current between source and drain in such a transistor is controlled by means of a depletion region which is induced in the channel by the voltage at the gate. At higher voltages, the operation may be hampered by the generation of minority charge carriers (holes in the case of an n-channel transistor), which form an inversion layer below the gate and screen off the latter from the channel, so that it is no longer possible inter alia to bring the transistor into the pinch state. To prevent an inversion occurring below the gate, the patent document U.S. Pat. No. 4,868,620 proposes the provision of a discharge for minority charge carriers in the form of a p-type surface zone. A suitable low voltage is applied to this zone via an electrical connection such that holes are removed across the blocked pn junction. To prevent punch-through between this discharge zone and the subjacent p-type substrate, a strongly doped n-type buried layer is provided below the zone between the epitaxial layer and the substrate, screening off the substrate from the epitaxial layer locally.
The zone forming a discharge for minority charge carriers in this known transistor is provided in the current path between source and drain and accordingly influences various electrical properties of the transistor to a non-negligible degree, for example its resistance, which is undesirable from a viewpoint of design technology. In addition, the construction of the transistor requires the availability of an epitaxial layer because of the presence of a buried layer, which means that it is not or hardly possible to provide the semiconductor layer, for example, in the form of an implanted layer.